The present disclosure relates generally to computer processor operation, and more specifically to improving the efficiency of processor pipeline sampling.
In computer processor applications, a “pipeline” or “pipe” is a set of data processing elements connected in series, wherein the output of one element in the series is the input of the next element in the series. In a contemporary pipeline sampler, information/data about the activity within a processor pipeline is sampled/collected at periodic, predetermined intervals, and the information is recorded for later processing. Sampling is typically initiated by a sampling pulse. To conserve processor resources, the data collection or sampling time of an individual sampling pulse, as well as the intervals between sampling pulses, are typically kept within set limits.
The sampled pipeline activity information is provided to a pipeline analysis algorithm for analysis of the pipeline's performance. In its simplest form, a contemporary pipeline analysis algorithm can utilize just a few bits of sampled information to derive basic pipeline performance characteristics such as cache pipeline utilization. More advanced contemporary pipeline analysis algorithms can use sampled information to derive broader pipeline performance characteristics such as request rates for individual fetch types and detailed information about system contention and pipeline recycle rates, thereby providing insight into how a given workload's behavior intersects with the system under test.
The usable sampled pipeline data occurs when the pipeline is active. If the pipeline is idle during sampling, substantially all of the sampled data fields will be inherently zero or inactive. Accordingly, only a subset of the available sampling time generates usable information for the pipeline analysis algorithm.